XMC Virtex 7 ADC board high performance FPGA based data acquisition and processing card

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Introduces CommAgilities New: XMC-V7-8ADC

CommAgility is introducing its new XMC Virtex 7 ADC board.   Below if an overview of our new board: The XMC-V7-8ADC is a new high performance FPGA based data acquisition and processing card from CommAgility in the extremely compact VITA 42.0 Express Mezzanine Card form factor. It is powered by the latest Xilinx Virtex-7 FPGA, and ideal for a range of applications including communications, Radar, software radio or data acquisition. As standard, a Virtex-7 X415T-2 FPGA is used, giving extensive resources for processing of the captured data including over 2000 DSP slices and 31MB of block RAM. In addition, substantial external DDR3 SDRAM is provided, which is organized as one 64-bit, 2GB bank for sample data storage, plus a separate 16-bit, 512MB bank to allow an embedded processor to be used in the FPGA. The card includes 8 x 250 MSps, 16 bit ADC channels to give class leading data acquisition performance, with an external clock and trigger for synchronization and an on-board zero delay PLL for flexible sampling control and phase alignment across multiple cards. The FPGA self-configures from Flash memory, which can store up to 3 customer images as well as a backup image which is used for card testing and Flash upgrade. The boot image is selectable over the I2C bus. The standard FPGA image includes a Microblaze processor with control and setup software, data sampling from the ADCs into SDRAM buffers, and data access over SRIO or PCIe, all using standard Xilinx IP cores. Full source code is provided, allowing customers to re-use as much or as little of this code as is needed. This also allows additional processing to be added as required, with no constraints imposed on the dataflow or processing architecture. Using this approach, maximum performance and flexibility is available for the application developer

Features 8 x 16 bit ADCs at up to 250 MSps sampling rate gives an industry leading data acquisition capability Xilinx Virtex-7 X415T-2 FPGA plus DDR3 SDRAM for high end processing capabilities, with multiple FPGA boot images in Flash PCI Express, SRIO and LVDS backplane connections give maximum flexibility and performance for the carrier interface Example FPGA code for management and data acquisition is provided as full source code to allow customers complete application control SOFTWARE/FIRMWARE FPGA: Example/default build with Micro-blaze processor, software libraries and high-speed dataflow architecture covers: ·         ADC setup and control ·         Sampling data to SDRAM with FIFOs and hooks for processing algorithms ·         Reading data from SDRAM to Host over PCIe or SRIO ·         Power on self-test and functional test ·         Flash image upgrade Management: I2C management inter-face For More Information contact Tony Cestone tony@newtecreps.com 301-937-6822

Hardware Specifications FPGA: ·         Xilinx Virtex-7, FFG1158 package ·         Standard option is X415T-2; others possible, maximum size X690T ·         2 Gbyte x64 DDR3-1600 SDRAM ·         512 Mbyte x16 DDR3-800 SDRAM ·         128 Mbyte configuration FLASH holds up to four FPGA and software images Backplane I/O: ·         PCI Express Gen3 x8 link to P15 ·         Dual SRIO Gen2 x4 links to P16 ·         16 LDVS pairs to P14 ·         I2C management bus to P15 Data acquisition: ·         8 input channels ·         Sampling rate up to 250 MSps ·         16 bit ADCs (TI ADS42JB69) ·         Full-scale input 2V p-p into 50 ohms ·         Input 3dB frequency range 10-650 ·         Transformer coupled inputs Clocking: ·         On-board zero delay PLL and jitter cleaner with VCXO, for flexible sample rate selection and phase alignment ·         Front panel input for reference clock ·         Front panel trigger input Front panel I/O: ·         8 input channels: SSMB connectors ·         Clock and Trig: SSMB connectors Form Factor: ·         Single-width Express Mezzanine Card ·         VITA 42.0 compliant Debug: ·         FPGA JTAG debug port